In recent years, along with an increasingly high level of integration of a semiconductor memory device, an LSI element configuring the semiconductor memory device has been getting more and more miniaturized. A ReRAM (Resistive RAM) that utilizes as memory a variable resistance element whose resistance value is reversibly changed, has been proposed as this LSI element. The ReRAM includes a memory cell array in which the variable resistance element is provided at intersections of word lines that extend in a direction along a substrate surface and are stacked in a direction intersecting the substrate surface and bit lines that extend in the direction intersecting the substrate surface.
In the ReRAM, a bit line select transistor for driving the bit line is provided between the substrate and a lower end of the bit line. Moreover, in a conventional ReRAM, a word line select transistor for driving the word line was provided upwardly of the memory cell array. Therefore, formation of the bit line select transistor and formation of the word line select transistor ended up being separate steps.
Moreover, contrary to the case of the bit line select transistor connected to the lower end of the bit line, it was required to provide a lead-out wiring line connecting the word line and the word line select transistor.
Furthermore, in order to connect the lead-out wiring line and the word line, it was required to provide a terrace-shaped contact part at a word line end, and there was a problem that area of the contact part increased along with an increase in the number of layers of word lines stacked in the direction intersecting the substrate surface, leading to increasing size of the device.